I'm gratified to see the growing interest in the Scope Junction open-source high-performance oscilloscope (SJOSHPO) concept. You've already stepped forward with ideas ranging from ADC selection to system design and approach. Great -- let's keep going!
People have asked for block diagrams, so here's what I've got so far. There are still other options we can explore. A comment on the original blog suggested a more distributed approach -- each channel having a small daughtercard with a local AFE (analog front-end), ADC, FPGA, and memory.
This is definitely worth considering. In fact, at the Tek Scope Tour I recently attended (unfortunately, not in Europe; ah, here's the North American page), the FAE explained that this is precisely the architecture used in the MDO & MSO series (though with custom silicon -- sigh).
Scope block diagram -- stand-alone version.
The signal generator block serves as such, and also as a calibrator, and a source of fast edges for TDR functionality. Basic VNA operation should also be possible.
I've added "dither" to the AFEs to support high-res acquisition modes. Although advanced triggers will be handled by the FPGA, I think a quality analog trigger is still required. This is one area I haven't given much thought to yet. How do we correlate the trigger time with the asynchronous sampling clock?
The LA (logic analyzer) inputs are pretty straightforward I think.
The more I think about a physical control panel with lots of knobs and switches, the less value I see in it. Even though our UI Poll was overwhelmingly in favor of this old-school approach, I think it's possible to make an even better virtual control panel once we have enough screen real estate to play with, and use nice tricks like auto-hiding. Throw in basic voice-recognition (yes, that one is dear to my heart), and we'd likely have a killer UI. What do you think?
HDMI seems the best video connection method, though it can be difficult getting hold of non-HDCP chips (which don't require a license). But they're around -- I've used both.
Buffer RAM performance concerns me, as FPGA DDR controllers usually sport substandard specs. Perhaps stealing one of a Zynq CPU's DDR3 controllers would be a useful hack. Then again, looking at the performance of, say, a Kintex-7, indicates my knowledge might be out of date. Good!
The USB module block diagram is not too different:
Scope block diagram -- USB module version.
The USB connection has migrated from the "front-end" (keyboard, mouse...) to the "back-end," connecting to the host system. The processor(s) can be lower performance, and video is no longer needed.
Please continue the discussion below. Key points: architecture, module vs. all-in-one, trigger/sampling sync, and UI.