The following anecdote describes an early experience of mine while working in the engineering trenches of a major scope manufacturer. This happened three decades ago, and that will explain some of the limitations of the algorithm and its implementation.
The scope in question was an early digitizing model that featured eight-bit A-D converters on the input channels. One of the newer features was the ability to do digital averaging of the signal, which, for a repetitive trace, offered improvement both in the displayed signal and the signal-to-noise ratio (SNR) of the waveform captured and processed in memory.
The computation was done by the scope's resident "waveform processor", which basically featured eight-bit arithmetic. The decision was made to restrict the number of averages to powers of 2 (2, 4, 8, and so on up to 256). This allowed the division in the algorithm to be performed by a simple right-shift and saved a great number of cycles in the computation.
The issue that reared its head, very late in the day in terms of the scope’s design cycle, was the following. I was summoned to the lab where the prototype code had been running for a couple of days, and they were observing a curious phenomenon. In this new averaging mode, as the user increased the number of averages of a noisy waveform, one would expect to see an increasingly cleaner signal, all the way up to 256 averages. What was observed, however, was that the waveform did get visually cleaner up to a point, after which flat portions started appearing in the waveform, making it look distorted.
Suffice to say, the results did not look very pleasant as one increased the number of sweeps averaged, and they were sure there was no correlated noise in the system that would explain what was being seen.
As I was very familiar with digital filters even in those early days, it appeared immediately as some sort of a limit cycle phenomenon caused by finite word length in the arithmetic. Sure enough, investigation of the algorithm and implementation pointed to the causes of the problem. There were at least two effects at play.
Firstly, the implementation kept a running sum for each point to implement the average, and as a new point came in, it used the difference in values to update the sum. This meant that at each point in the waveform, you had a recursive digital filter -- i.e., one with a single pole -- which meant that it was indeed prone to limit cycles or dead bands. Secondly, the implementation of the divide, by a shift-and-truncate operation with eight-bit arithmetic, meant that the first-order recursive digital filter exhibited limit cycles the moment the divisor (power of 2) became large, and the dead bands showed up as flat areas on the waveform.
Since double-precision arithmetic was not an option, we came up with some simpler solutions involving a mix of rounding operations and some dithering, and we were able to keep the core of the firmware intact. Subsequent generations of scopes, of course, had much more powerful DSP hardware, so this particular issue did not crop up again -- to my knowledge.
jsalsburg 4/13/2012 2:47:37 AM User Rank Apprentice
Re: Dither, Flatness
My memory did not serve me well, the Chip I remember was from TRW, (now Northrop-Grumman). It was physically large and definitely was for a dark Military purpose. It used a triple-diffused bipolar process to build more complex functions, such as the 16x16 multiplier (MPY 16), used together with the AMD 2901 bit-slice processor for video and defense applications in the late-1970s.
To make an FFT Processor from these Chips required a bit reverse and Radix circuit to be added. This was real hardcore DSP.
I actually drove to TRW (Space Park) sometime in 1979 and requested Datasheets face to face, surprisingly they gave them to me over the counter.
I do recall reading papers or articles about AT&T's DSP1.
The NEC 7720 also rings a bell, and reminded me of a very odd chip they later released, called a dataflow processor. I don't think I ever quite grokked that one, but I probably still have a datasheet in my files!
According to Wikipedia Shiv, you have some claim on the prize, but those weren't the answers I was looking for!!! ;-)
Jay mentions a Fairchild FFT chip. I don't have any specific memory of this, though I do recall various Fairchild chips (bit-slice?) aimed at fast processing. Does the name MicroLogic ring a bell? I think it was also Fairchild who produced a (not fast) 1-bit processor! Sortof a ladder-logic replacement...?
Okay, the chip I have in mind as the first DSP is the Intel 2920. I think it had onboard ADC & DAC. The biggest problem was its lack of a multiplier! Ooops.
Here's a Wikipedia excerpt:
in 1978 they (TI) produced the first Speak & Spell, with the technological centerpiece being the TMS5100[3], the industry's first digital signal processor. It also set other milestones, being the first chip to use Linear predictive coding to perform speech synthesis.[4].
In 1978, Intel released the 2920 as an "analog signal processor". It had an on-chip ADC/DAC with an internal signal processor, but it didn't have a hardware multiplier and was not successful in the market. In 1979, AMI released the S2811. It was designed as a microprocessor peripheral, and it had to be initialized by the host. The S2811 was likewise not successful in the market.
I doubt the Speak&Spell chip can be considered a DSP. I'm pretty sure it just implemented LPC decoding. I don't recall it as being programmable in any real sense, though I may be wrong...
I recall the AMI S2811, but nothing in detail. Again, the datasheet may still be lurking here.
I am also reminded of some amazing Reticon chips - analog CCD technology that did discrete-time signal processing operations. I believe they had convolution/correlation chips (e.g., FIR filters), and also a part that somehow performed a Chirp-Z transform (I'm picturing a photomicrograph of a swept sine wave pattern of electrodes)!!!!!
And if anyone cares, I designed (but never built) my own DSP board ca. 1980. It used a 16 bit MAC, a multiport register file, a bit-slice sequencer, data DRAM, and instruction SRAM about 136 bits wide! It would have run at 10MHz, but be able to do about 5 operations per cycle. Fun times.
jsalsburg 4/9/2012 2:38:02 AM User Rank Apprentice
Re: Dither, Flatness
If memory serves me correctly, my first recollection of a DSP Chip was from Fairchild around 1979-80, was a rather large 64 pin DIP, and was designed to run FFT requiring significant outboard support chips, memory, bus controllers, etc. It was applied to some dark Military purpose.
@jsalsburg, indeed you are correct, the prime examples being the Motorola 56K parts with 24- and 48-bit datapaths and 56-bit accumulators. The NEXT machines used them I believe, with excellent audio.
jsalsburg 4/7/2012 10:25:54 PM User Rank Apprentice
Re: Dither, Flatness
In the mid 1980s when Large Scale DSPs started appearing they were all INTEGER-based and had Headroom Problems, but they spawned many high-end products like those form Eventide. Propagation of Monolithic DSPs into Scopes was delayed, at least for affordable Scopes, because of the very reason expressed, the lack of headroom in recursive algorithms. When Floating Point and 24-bit DSPs appeared and then were incorporated into Scopes, this performance problem was eliminated, allowing highly recursive algorithms to live without the distortion of the waveform caused by small Bit-Magnitudes.
It's a curse, Womai, for Digitizing scopes -- they are still suspect even though the new ones afe far superior to the best-in-class Tek Analog scopes of yore!
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